HARDWARE LAB 19 · MEMORY EXPANSION

CARTRIDGE BUS
+ BANK SWITCHING

Hold the CPU address steady, change one mapper register, and watch a different physical ROM bank appear in the same address-space window.

01 CPU ADDRESS02 ADDRESS DECODER03 BANK REGISTER04 PHYSICAL ROM BYTE05 DATA BUS

LIVE BUS PROBE

Address, data, and active-low control lines

BUS IDLE

Cycle 0. BUS IDLE. Address 0x9234. Data floating. Bank 0. /RD INACTIVE. /WR INACTIVE. /ROM_CS INACTIVE. /MAPPER_CS INACTIVE.

ADDRESS BUS · 0x92341001001000110100

A151A140A130A121A110A100A91A80A70A60A51A41A30A21A10A00

DATA BUS · --HIGH-Z / FLOATING

D7ZD6ZD5ZD4ZD3ZD2ZD1ZD0Z

/RD1INACTIVE

/WR1INACTIVE

/ROM_CS1INACTIVE

/MAPPER_CS1INACTIVE

Data-bus driver: NO DEVICE / HIGH-Z. A slash means the signal is active at logic 0.

ADDRESS DECODE

CPU-visible address → physical ROM address

SWITCHABLE 16 KiB WINDOW

CPU ADDRESS0x9234SELECTED BANK0ROM OFFSET0x1234BYTE VALUE0x7C

0 × 0x4000 + 0x1234 = 0x01234

CPU ADDRESS SPACE

One fixed window, one switchable window

128 KiB PHYSICAL ROM / 32 KiB VISIBLE

0x0000–0x5FFFSYSTEM / NOT MODELEDCartridge chip select stays inactive

0x6000MAPPER WRITE REGISTERCPU data D2…D0 loads the bank latch

0x6001–0x7FFFUNMAPPED HEREGeneric teaching circuit

0x8000–0xBFFFSWITCHABLE → BANK 0The same CPU address can resolve to eight ROM locations

0xC000–0xFFFFFIXED → BANK 7Stable code remains reachable after every mapper write

BANK 00x00000–0x03FFFSWITCH WINDOW

BANK 10x04000–0x07FFFOFF BUS

BANK 20x08000–0x0BFFFOFF BUS

BANK 30x0C000–0x0FFFFOFF BUS

BANK 40x10000–0x13FFFOFF BUS

BANK 50x14000–0x17FFFOFF BUS

BANK 60x18000–0x1BFFFOFF BUS

BANK 70x1C000–0x1FFFFFIXED WINDOW

SAFE FETCH SCRIPT

Prove what changes—and what does not

0 / 7 OPS

01WRITE BANK 1Select ROM bank 1
02READ 0x9234Read switchable window
03WRITE BANK 5Select ROM bank 5
04READ 0x9234Read same CPU address again
05READ 0xD234Read fixed window
06WRITE BANK 2Select ROM bank 2
07READ 0xD234Re-read fixed window

DIAGNOSTIC CHALLENGE

COMPARE BOTH WINDOWS

Read one switchable address through two banks, then read one fixed-window address through two banks.

01SWITCH WINDOW CHANGESSame CPU address; different bank, physical address, and byte.

02FIXED WINDOW HOLDSSame CPU address, physical address, and byte across mapper writes.

The safe script completes this diagnostic, or reproduce it manually with the address field and bank-write buttons.

BUS TRACE

Every address, strobe, sample, and release

#	CYCLE	PHASE	OP	CPU ADDR	DATA	/RD	/WR	/ROM	/MAP	BANK	ROM ADDR
No transactions yet. Step a CPU read or write a bank register.